The invention pertains to a comparison circuit for an analog/digital converter. The comparison circuit comprises a network of comparators each comparing an analog voltage to be converted with a reference voltage. The analog voltage to be converted generally arises from a sample-and-hold module allowing the whole assembly of comparators of the network to receive the same analog voltage at the moment at which they perform the comparison with the reference voltage.
The reference voltages received by the comparators are distributed over a range in which the analog voltage can vary. The distribution is generally uniform over the range and it is for example obtained by means of a network of resistors, all of like value and linked in series between the terminals of a source of supply voltage of the comparator. There are substantially as many resistors as comparators. The reference voltages are then tapped off at the various inter-resistor junction points.
Each comparator comprises two outputs, one direct and the other inverse. The voltages present on its outputs are dependent on the potential difference between the analog voltage and the reference voltage received by the comparator concerned. FIG. 1 represents three curves showing the variation in the voltage present on the direct output On−1, On and On+1 as a function of the analog voltage V, for three comparators C of rank n−1, n and n+1 in the network of comparators. These three comparators receive respectively reference voltages Vref n−1, Vref n and Vref n+1. The comparators receive reference voltages similar in their distribution over the range.
For a given comparator, for example the comparator of rank n, if its response were perfect, the voltage On present on its direct output ought to be zero when the analog voltage V is equal to the reference voltage Vn. However, the response of the comparators is not perfect and a voltage mismatch, termed the offset voltage, is noted between the reference voltage Vref n and the analog voltage V causing a zero voltage On on the direct output of the comparator of rank n. In practice it is noted that each comparator C has its own offset voltage independent of that of the other comparators. In FIG. 1, the comparator C of rank n−1 has an offset voltage Offset n−1, the comparator C of rank n has an offset voltage Offset n and the comparator C of rank n+1 has an offset voltage Offset n+1. The offset voltages may be negative or positive. Their values are randomly distributed for the various comparators of an analog/digital converter. These offset voltages impair the accuracy of the converter and it is noted that they tend to increase when the size of the electronic component on which the converter is made is reduced.
Additionally, the resolution LSB of an analog digital converter may be expressed by the mismatch in the analog voltage modifying the value of a low-order bit at the output of the converter. The LSB resolution is expressed as follows:
  LSB  =            Vpeak      /      peak              2      n      where Vpeak/peak represents the maximum amplitude of the analog voltage that the converter can convert, and where n is the number of comparators in the network. If the resolution LSB is less than three times the offset voltage, there is a loss of linearity of the converter and the low-order bit is no longer meaningful.